Field of the Invention
The present invention relates to a semiconductor manufacturing technique, and more specifically, to method of manufacturing a semiconductor device for treating a surface of an SiC substrate before epitaxial growth.
Description of the Related Art
In recent years, power semiconductors for power control or supply have been used in many fields such as electric and electronic equipment, home electric appliances, and electric cars. Many of the power semiconductors conventionally consist of Si (silicon) semiconductors. In recent years, much effort has been made to examine the use of SiC (silicon carbide) semiconductors that can withstand higher voltages than Si semiconductors and that enable, for example, a reduction in power loss and in the size of power converters. Many polytypes of SiC exist such as 3C-SiC that is a cubic system and 4H-SiC and 6H-SiC that are hexagonal crystal systems. Among these polytypes, 4H-SiC is typically used to produce practical SiC semiconductor devices.
FIG. 1 depicts an example of a conventional SiC_PN diode. An SiC_PN diode 100 in FIG. 1 includes a cathode electrode 101 formed of Ni, an n+ type SiC substrate 102 formed of a 4H-SiC crystal, and an n− type epitaxial layer (drift layer) 103 epitaxially grown on the SiC substrate 102 so as to have a film thickness corresponding to a withstand voltage. The SiC_PN diode 100 further includes JTE areas 104 and 105 formed on a front surface of the epitaxial layer 103 away from each other, a p+ layer 106 formed on the epitaxial layer 103 at a central portion thereof, an anode electrode 107 provided on the P+ layer 106 and formed of Ti/Al, and SiO2 films 108 and 109 formed on the JTE areas 104 and 105, respectively, as insulating films. The SiC substrate 102 has a dielectric breakdown voltage that is 10 times as high as the dielectric breakdown voltage of an Si substrate to enable the film thickness of the epitaxial layer 103 to be reduced to 1/10 compared to Si. Consequently, the SiC substrate 102 allows implementation of a PN diode with a higher withstand voltage and a lower resistance than Si.
The SiC substrate 102, which is a single crystal substrate, includes crystal defects such as point defects and extended defects. The extended defects include threading screw dislocation (TSD), threading edge dislocation (TED), basal plane dislocation (BPD), and stacking fault (SF). These crystal defects (BPD and SF) are known to propagate from the SiC substrate 102 to the epitaxial layer 103.
FIG. 2 is a conceptual drawing illustrating a state where basal plane dislocation (BPD) has occurred inside the SiC substrate 102 in FIG. 1 and propagated to the epitaxial layer 103. The BPD has developed along a basal plane. The SiC epitaxial layer 103 is formed on the front surface of the SiC substrate 102 through crystal growth (step flow growth). At this time, the epitaxial layer 103 is grown on planes created by tilting the SiC substrate 102 through an angle of 10° to the basal plane so as to intentionally increase step density. The angle of the front surface tilted with respect to the basal plane 200 is designated as an off angle θ. A large number of BPDs occur inside the SiC substrate 102 and propagate to the epitaxial layer 103 grown on the front surface of the SiC substrate 102. The “basal plane” is a general term for planes perpendicular to a C axis of silicon carbide and includes a (0001) face (also referred to as an “Si face”) and a (000-1) face (also referred to as a “C face”). Faces perpendicular to the a axis (an axis perpendicular to the C axis) of silicon carbide (faces parallel to the C axis) are generally referred to as “a faces”. The a faces include, besides a (11-2) face, a (2-1-10) face, a (−12-10) face, a (−2110) face, a (−1-120) face, and a (1-210) face.
The BPDs propagated to the film of the epitaxial layer 103 cause stacking faults that are stable in terms of energy. Here, the stacking fault refers to a lattice fault formed by out-of-order stacking of atomic planes of the crystal. A typical stacking fault is a single Shockley stacking fault (SSF). The SSF refers to a structure in which one layer of stacking fault is inserted into a 4H-Si crystal (a hexagonal structure including four layers). The SSF behaves like a quantum well with respect to a <0001> direction of the 4H-SiC crystal and thus captures and traps electrons. In other words, the stacking fault acts as a lifetime killer to increase on resistance. When the SSF increases to make the resistance of the power semiconductor device high, a phenomenon occurs in which, with a constant voltage, a forward current decreases over time. The SSF occurs and grows using the BPD as a nucleus, and thus, a reduction in BPD is essential for suppressing an increase in SSF.
To reduce the BPD in the epitaxial layer 103, two methods have been proposed which are referred to as “low-off-angle growth during epitaxial deposition” and “KOH (potassium hydroxide) etching as a pretreatment for epitaxial growth” (for example, see Z. Zhang and T. S. Sudarshan. “Basal plane dislocation-free epitaxy of silicon carbide” Appl. Phys. Let. 87. 151913 (2005)).
In the former method, as is known, when the epitaxial layer is grown with the angle to the basal plane 200 (off angle θ) reduced, elastic energy needed to linearly grow the dislocation is calculated to have a very large value based on Expression (1).
                    W        =                  E                      cos            ⁢                                                  ⁢            α                                              Expression        ⁢                                  ⁢                  (          1          )                    
Here, W denotes elastic energy needed to linearly grow the dislocation, and E denotes elastic energy of the fault, and α denotes an angle between a film growth direction and a dislocation line. The film growth direction coincides with a normal direction of the front surface of the substrate.
FIGS. 3A and 3B are diagrams illustrating a method for reducing the basal plane dislocation (BPD) based on the off angle. FIG. 3A illustrates a case of a large off angle, and FIG. 3B illustrates a case of a small off angle. As depicted in FIG. 3A, when the off angle θ is large and the angle α between the growth direction of the epitaxial layer and the dislocation line of the BPD is small, W is calculated to have a small value based on Expression (1). Consequently, the energy needed to extend the basal plane dislocation is low, facilitating growth of the basal plane dislocation in the epitaxial layer 103.
In contrast, when the off angle θ is small and the angle α is large as depicted in FIG. 3B, W is calculated to have a large value based on Expression (1). Consequently, the energy needed to extend the basal plane dislocation is high, hindering growth of the basal plane dislocation in the epitaxial layer 103. When the off angle θ is small, the probability that the BPD present in the SiC substrate 102 is converted into TED (Threading Edge Dislocation) increases, enabling a reduction in faults resulting from the BPD in the epitaxial layer 103. Compared to the BPD, the TED less seriously affects the SiC semiconductor device. Thus, reducing the BPD is important.
In the latter method in Z. Zhang and T. S. Sudarshan. “Basal plane dislocation-free epitaxy of silicon carbide” Appl. Phys. Let. 87. 151913 (2005), as is known, the BPD can be selectively etched, and thus, the off angle can be made locally small, preventing the BPD from growing during the subsequent epitaxial growth.
However, in the former method, a simple attempt to reduce the off angle θ suppresses step growth during the epitaxial growth, making crystal growth based on two-dimensional random nucleation dominant. Thus, disadvantageously, no high-quality 4H-SiC crystal is obtained. Further, disadvantageously, step bunching is formed on the front surface of the epitaxial layer 103. Here, the step bunching refers to a phenomenon in which, during the process of the epitaxial growth, each atomic layer grows transversely with respect to a growth direction of the atomic layer, so that growth steps at ends of the atomic layers are united together under a certain condition, resulting in a significantly irregular front surface of the epitaxial layer 103.
Furthermore, in the latter method, the KOH etching with growth of the BPD inhibited involves a large etching depth of 7 μm. This corresponds to 70% of the film thickness of 10 μm of the epitaxial layer 103 at which the epitaxial layer 103 can withstand a voltage of 1.2 kV. In manufacture of the semiconductor device, such a local variation in film thickness reduces the withstand voltage in some areas of the semiconductor device, making the manufacturing process for the semiconductor device invalid. Moreover, the use of KOH leads to alkali contamination of the device. For these reasons, it is disadvantageously difficult to adopt application of the KOH etching treatment to the SiC substrate 102 before epitaxial growth, as an industrial process.